Recent improvements for substrate to substrate or wafer bonding are increasingly important in 3D IC structures. Wafer bonding is increasingly used to provide increased integration by forming vertical stacks of semiconductor devices without the need for intervening structures such as substrates or circuit boards. By bonding wafers directly, a single packaged integrated circuit may be produced which includes two or more wafer layers, providing increased system on a chip capabilities. In one particular application of wafer bonding, an array of image sensors is formed on one wafer and bonded to an image sensor circuit wafer, to provide an integrated image sensor system in a single packaged device.
Wafer to wafer bonding approaches known previously include oxide-oxide or fusion bonding, and metal to metal bonding using thermocompression bonding at higher pressure and high temperatures. These prior approaches induce high mechanical and thermal stress on the devices, or fail to provide needed metal-to-metal connections.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.